This application claims the priority of Korean Patent Application No. 2002-55005, filed on Sep. 11, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device having an etch stopper formed of a silicon nitride (SiN) layer by low-temperature atomic layer deposition (ALD) in a self-aligned contact (SAC) process and a method for fabricating the semiconductor device.
2. Description of the Related Art
As a finer pattern and a thinner film are required in a process of fabricating semiconductor devices, atomic layer deposition (ALD) technology beneficial for the finer pattern and the thinner film is more widely applied to DRAM devices. In particular, ALD is useful for accurately controlling the thickness of a film and thus is used to form capacitor dielectric films, diffusion barriers, gate dielectric layers, and the like.
As semiconductor devices become highly integrated, the space between gates becomes smaller, and thus a self-aligned contact (SAC) process having a design rule for the space of about 0.2 μm has been generally used. The SAC process uses a gate pattern as an etch buffer so as to cause a short between a contact plug and the gate pattern due to a misalignment when a contact hole is formed in a source or a drain between gates. As a technique using the SAC process is introduced into a method of fabricating the semiconductor device, a process related to the SAC process is changed accordingly.
FIG. 1 is a sectional view illustrating the SAC process according to the conventional art after a second etching is performed, and FIG. 2 is a enlarged view of area A of FIG. 1.
Referring to FIG. 1, a gate pattern 20 is formed on a semiconductor substrate 10, and an etch stopper 30 is deposited on the gate pattern 20. Then, an interlayer insulating film 40 is formed on the gate pattern 20 and the semiconductor substrate 10, and the interlayer insulating film 40 is planarized. A photoresist pattern 50 is formed on the interlayer insulating film 40, and a self-aligned contact hole 60 is formed by dry etching, exposing a source region and a drain region of the gate pattern 20.
In the dry etching for forming the self-aligned contact hole 60, an oxide film or a nitride film having a high etching selectivity with the interlayer insulating film 40 formed of oxide film and formed by low pressure chemical vapor deposition (LPCVD) is used as an insulating pattern 26 on the upper side of the gate and a gate spacer 28 so as to prevent a gate electrode pattern 22 and a silicide pattern 24 of the gate pattern 20 from being etched.
In addition, when the self-aligned contact hole is dry etched, the nitride film formed by LPCVD is used as the etch stopper 30 so as to prevent damage to the semiconductor substrate 10 from etching. The etch stopper 30 is a thin film having a thickness of 100-200 Å and is removed by a second dry etch of which the etching conditions are different from the etching conditions of the dry etch for forming the self-aligned contact hole, after dry etching the interlayer insulating film 40 to form the self-aligned contact hole.
However, in a second dry etching for the thin etch stopper 30 of the conventional self-aligned contact process, the semiconductor substrate 10 is also etched, and thus a recess in or damage to the semiconductor substrate 10 results, as shown in FIG. 2. This is because the film to be etched is very thin, and a constant etching speed for the whole wafer is not yet possible. Further, the thickness of the nitride film cannot be controlled to be constant. In addition, since there are differences among equipment used for mass production, it is difficult to consistantly etch thin films, a fact which causes further damage to semiconductor substrates.
Damage to the semiconductor substrate 10 or a recess therein can cause AC parameter defects such as TRDL (last data in to row precharge) in the DRAM device chip at the center of the wafer which has been etched less while degrading the refresh characteristics at the edge of the wafer which has been etched more. Thus, reliability and yield of the semiconductor device are reduced.